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Cadence errors and their descriptions

Contents 1 Verilog 2 VerilogA 3 Simulation, 4 Mixed Signal Simulation

VerilogEdit

• Error

In Verilog-M... not found in test fixture vermix

Solution

Exit, and delete the sim folder, there is left over crap

• Error

... not found in map / current

Solution

verilog and symbol pins do not match

• Error

USRWARN: You have used nondetailed Interface Element (IE) Generation USRERR: MS simulation does not support bidirectional interface element

generated by terminal bin<0> of instance I7

Solution

Verilog block has a port define as Input or Output, and a port in the hierarchy that is connected to the verilog port is defined inoutOuput

VerilogAEdit

• Error

Unexpectedly low amplitude using ideal opamps.

Solution

The gain of the opamp to low, increase it

Simulation, Edit

• Error

Bulk-drain source junction current exceeded Imax

Solution

in a mosfets W or L you forgot the unit u

Mixed Signal SimulationEdit

• Error

Unknown cell type functional

Solution

Change simulator to spectreverilog

• Error

Netlist Error: Partitioning-- Must correct partitioning errors before continuing with netlisting.

Solution

Stop list and Mixed Signal/Partition option must contain the same views

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